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this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev. 1.0 / apr. 2006 1 16mb synchronous dram based on 512k x 2bank x16 i/o document title 2bank x 512k x 16bits synchronous dram revision history revision no. history draft date remark 0.1 initial draft feb. 2006 preliminary 1.0 final revision apr. 2006
rev. 1.0 / apr. 2006 2 11 synchronous dram memory 16mbit (1mx16bit) hy57v161610ft(p)-xx(i) series description the hynix hy57v161610f-series is a 16,777,216-bits cmos synchronous dram, ideally suited for the main memory and graphic applications which require large memory dens ity and high bandwidth. hy57v161610f-series is organized as 2banks of 524,288x16. hy57v161610f-series is offering fully sync hronous operation referenced to a posi tive edge clock. all inputs and out- puts are synchronized with th e rising edge of the clock input. the data paths are internally pipelined to achieve very high bandwidth. all input and output voltage levels are compatible with lvttl. programmable options include the length of pipeline (read latency of 1,2 or 3), the number of consecutive read or write cycles initiated by a single control command (burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). a burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new bu rst read or write command on any cycle. (this pipeline design is not restricted by a '2n' rule.) features ? voltage: vdd, vddq 3.3v supply voltage ? all device pins are compatible with lvttl interface ? jedec standard 400mil 50pin tsop-ii with 0.8mm of pin pitch (lead or lead free package) ? all inputs and outputs refere nced to positive edge of system clock ? data mask function by udqm, ldqm ? internal two banks operation ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4, 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency; 1, 2, 3 clocks ? burst read single write operation ordering information (v dd (min) of hy57v161610ft(p)-5(i) series is 3.15v) note: 1. hy57v161610ftp series: le ad free, commercial temperature(0 o c ~ 7 0 o c .) 2. hy57v161610ft series: leaded, commercial temperature(0 o c ~ 7 0 o c .) 3.HY57V161610FTP-XXi series: lead free, industrial temperature(-40 o c ~ 85 o c ) 4.hy57v161610ft-xxi series: leaded, industrial temperature(-40 o c ~ 85 o c ) part no. clock frequency organization interface package hy57v161610ft(p)-5(i) 200mhz 2banks x 512kbits x16i/o lvttl 400mil 50tsopii hy57v161610ft(p)-6(i) 166mhz hy57v161610ft(p)-7(i) 143mhz hy57v161610ft(p)-h(i) 133mhz
rev. 1.0 / apr. 2006 3 11 synchronous dram memory 16mbit (1mx16bit) hy57v161610ft(p)-xx(i) series pin configuration v dd dq0 dq1 vssq dq2 dq3 vddq dq4 dq5 vssq dq6 dq7 vddq ldqm /we /cas /ras /cs ba a10 a0 a1 a2 a3 vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 vss dq15 dq14 vssq dq13 dq12 vddq dq11 dq10 vssq dq9 dq8 vddq nc udqm clk cke nc a9 a8 a7 a6 a5 a4 vss 50pin tsopii 400mil x 825mil 0.8mm pin pitch
rev. 1.0 / apr. 2006 4 11 synchronous dram memory 16mbit (1mx16bit) hy57v161610ft(p)-xx(i) series pin description symbol type description clk input clock: the system clock input. all other in puts are registered to the sdram on the rising edge of clk cke input clock enable: controls internal clock sign al and when deactivated, the sdram will be one of the states among (deep) power down, suspend or self refresh cs input chip select: enables or disables all inputs except clk, cke, and dqm ba input bank address: select either one of banks during both ras and cas activity a0 ~ a10 input row address: ra0 ~ ra10, column address: ca0 ~ ca7 auto-precharge flag: a10 ras , cas , we input command inputs: ras , cas and we define the operation refer function truth table for details udqm, ldqm input data mask: controls output buffers in re ad mode and masks input data in write mode dq0 ~ dq15 i/o data input / output: mu ltiplexed data input / output pin v dd /v ss supply power supply for internal circuits v ddq /v ssq supply power supply for output buffers nc - no connection : these pads should be left unconnected
rev. 1.0 / apr. 2006 5 11 synchronous dram memory 16mbit (1mx16bit) hy57v161610ft(p)-xx(i) series functional block diagram 512k x 2banks x 16 i/o synchronous dram column addr. latch & counter burst length counter refresh interval timer refresh counter dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 address register i/o control test mode mode register self refresh counter column decoder sense amp & i/o gates 512kx16 bank 0 column decoder sense amp & i/o gates 512kx16 bank 1 ras cas cs we udqm ldqm cke precharge overflow column active row active address[0:10] clk ba(a11) state machine row decoder row addr. latch/predecoder auto/self refresh ref. addr.[0:11] data input/output buffers row addr. latch/predecoder
rev. 1.0 / apr. 2006 6 11 synchronous dram memory 16mbit (1mx16bit) hy57v161610ft(p)-xx(i) series basic functional description mode register ba a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 bank address 0 op code 0 0 cas latency bt burst length op code a9 write mode 0 burst read and burst write 1 burst read and single write burst type a3 burst type 0sequential 1interleave burst length a2 a1 a0 burst length a3 = 0 a3=1 00 0 1 1 00 1 2 2 01 0 4 4 01 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved cas latency a6 a5 a4 cas latency 0 0 0 r e s e r v e d 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 r e s e r v e d 1 1 0 r e s e r v e d 1 1 1 reserved
rev. 1.0 / apr. 2006 7 11 synchronous dram memory 16mbit (1mx16bit) hy57v161610ft(p)-xx(i) series absolute maximum rating note: 1. hy57v161610ftp series: lead free, commercial temperature(0 o c ~ 7 0 o c .) 2. hy57v161610ft series: leaded, commercial temperature(0 o c ~ 7 0 o c .) 3.HY57V161610FTP-XXi series: lead free, industrial temperature(-40 o c ~ 85 o c ) 4.hy57v161610ft-xxi series: leaded, industrial temperature(-40 o c ~ 85 o c ) dc operating condition (t a = 0 to 70 o c, t a = -40 to 85 o c, ) note: 1. all voltages are referenced to v ss = 0v 2. vih (max) is acceptable 4.6v ac pulse width with <=3ns of duration. 3. vil (min) is acceptable -1.5v ac pulse width with <=3ns of duration. 4. v dd (min) is 3.15v when hy57v161610ft(p)-7 operates at cas latency=2 5. v dd (min) of hy57v161610ft(p)-5 is 3.15v ac operating test condition (t a = 0 to 70 o c 4) , t a = -40 to 85 o c 5) ) note 1. see to output load circuit fig. 2. v dd (min) is 3.15v when hy57v161610et-7 operates at cas latency=2 and tck2=8.9ns 3. v dd (min) of hy57v161610et-5 is 3.15v 4. hy57v161610ft(p) series: leaded, commercial temperature(0 o c ~ 7 0 o c .) 5. hy57v161610ft(p)-xxi series: lead free, industrial temperature(-40 o c ~ 85 o c) parameter symbol rating unit note ambient temperature t a 0 ~ 70 o c commercial temp. -40 ~ 85 o c industrial temp. storage temperature t stg -55 ~ 125 o c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on vdd supply relative to vss v dd, v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1w soldering temperature . time t solder 260 . 10 o c . sec parameter symbol min typ max unit note power supply voltage v dd, v ddq 3.0 3.3 3.6 v 1, 4, 5 input high voltage v ih 2.0 3.0 v ddq+ 0.3 v 1, 2 input low voltage v il -0.3 - 0.8 v 1, 3 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4 / 0.4 v input timing measurement reference level voltage v trip 1.4 v input rise / fall time t r / t f 1ns output timing measurement reference level voltage v outref 1.4 v output load capacitance for access time measurement cl 30 pf 1
rev. 1.0 / apr. 2006 8 11 synchronous dram memory 16mbit (1mx16bit) hy57v161610ft(p)-xx(i) series capacitance (t a = 25 o c , f=1mhz) output load circuit dc characterristics i (t a = 0 to 70 o c 5) , t a = -40 to 85 o c 6) ) note : 1.v dd (min) is 3.15v when hy57v161610ft(p)-7 operates at cas latency=2 and tck2=8.9ns. 2.v dd (min) of hy57v161610ft(p)-5 is 3.15v 3.v in = 0 to 3.6v, all other pins are not under test = 0v 4. d out is disabled, v out =0 to 3.6v 5. hy57v161610ft(p) series: leaded, commercial temperature(0 o c ~ 7 0 o c .) 6. hy57v161610ft(p)-xxi series: lead free, industrial temperature(-40 o c ~ 85 o c ) parameter pin symbol min max unit input capacitance clk ci1 2.5 4.0 pf a0 ~ a10, ba, cke, cs , ras , cas , we , ldqm, udqm ci2 2.5 5 pf data input / output capaci tance dq0 ~ dq15 ci/o 4 6.5 pf parameter symbol min max unit note power supply voltage v dd 3.0 3.6 v 1, 2 input leakage current i li -1 1 ua 3 output leakage current i lo -1 1 ua 4 output high voltage v oh 2.4 - v i oh = -4ma output low voltage v ol -0.4v i ol = +4ma vtt=1.4v rt=250 30pf output dc output load circuit 30pf output ac output load circuit
rev. 1.0 / apr. 2006 9 11 synchronous dram memory 16mbit (1mx16bit) hy57v161610ft(p)-xx(i) series dc characteristics ii (t a = 0 to 70 o c 4) , t a = -40 to 85 o c 5) ) note : 1.v dd (min) is 3.15v when hy57v161610ft(p)-7 operates at cas latency=2 and tck2=8.9ns. 2.v dd (min) of hy57v161610ft-5 is 3.15v 3. i dd1 and i dd4 depend on output loading and cycle rates. spec ified values are measured with the output open. 4. hy57v161610ft(p) series: leaded, commercial temperature(0 o c ~ 7 0 o c .) 5. hy57v161610ft(p)-xxi series: lead free, industrial temperature(-40 o c ~ 85 o c ) parameter symbol test condition speed uni t not e 5 6 7 h operating current idd1 burst length=1, one bank active t rc t rc (min), i ol =0ma 130 120 110 110 ma 2 precharge standby current in power down mode idd2p cke v il (max), t ck = 15ns 2 ma idd2ps cke v il (max), t ck = 1 precharge standby current in non power down mode idd2n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 25 ma idd2ns cke v ih (min), t ck = input signals are stable. 15 active standby current in power down mode idd3p cke v il (max), t ck = 15ns 3.0 ma idd3ps cke v il (max), t ck = 3.0 active standby current in non power down mode idd3n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 50 ma idd3ns cke v ih (min), t ck = input signals are stable. 30 burst mode operating current idd4 t ck t ck (min), i ol =0ma all banks active cl=3 130 120 110 110 ma 3 cl=2 - 110 110 - auto refresh current idd5 t rc t rc (min), all banks active 130 110 110 110 ma self refresh current idd6 cke 0.2v 2 ma
rev. 1.0 / apr. 2006 10 11 synchronous dram memory 16mbit (1mx16bit) hy57v161610ft(p)-xx(i) series ac characteristics i (ac operating conditions unless otherwise noted) note: 1. assume t r / t f (input rise and fall time) is 1ns. if t r & t f > 1ns, then [(t r +t f )/2-1]ns should be added to the parameter. 2. access time to be measured with in put signals of 1v/ns edge rate, from 0.8v to 0.2v. if t r > 1ns, then (t r /2-0.5)ns should be added to the parameter. parameter sym- bol 5 6 7 h unit note min max min max min max min max system clock cycle time cl = 3 t ck3 5.0 1000 6.0 1000 7.0 1000 7.5 1000 ns cl = 2 t ck2 10 10 10 10 ns clock high pulse width t chw 2.0 - 2.0 - 2.0 - 2.5 - ns 1 clock low pulse width t clw 2.0 - 2.0 - 2.0 - 2.5 - ns 1 access time from clock cl = 3 t ac3 -4.5-5.4-5.4-5.4 ns 2 cl = 2 t ac2 -6.0-6.0-6.0-6.0 ns data-out hold time t oh 2.0 - 2.0 - 2.5 - 2.5 - ns data-input setup time t ds 1.5 - 1.5 - 1.5 - 1.5 - ns 1 data-input hold time t dh 0.8 - 0.8 - 0.8 - 0.8 - ns 1 address setup time t as 1.5 - 1.5 - 1.5 - 1.5 - ns 1 address hold time t ah 0.8 - 0.8 - 0.8 - 0.8 - ns 1 cke setup time t cks 1.5 - 1.5 - 1.5 - 1.5 - ns 1 cke hold time t ckh 0.8 - 0.8 - 0.8 - 0.8 - ns 1 command setup time t cs 1.5 - 1.5 - 1.5 - 1.5 - ns 1 command hold time t ch 0.8 - 0.8 - 0.8 - 0.8 - ns 1 clk to data output in low-z time t olz 1.0 - 1.0 - 1.5 - 1.5 - ns clk to data output in high-z time cl = 3 t ohz3 -4.5-5.4-5.4-5.4ns cl = 2 t ohz2 -6.0-6.0-6.0-6.0ns
rev. 1.0 / apr. 2006 11 11 synchronous dram memory 16mbit (1mx16bit) hy57v161610ft(p)-xx(i) series ac characteristics ii (ac operating conditions unless otherwise noted) note: 1. a new command can be given trrc after self refresh exit. parameter sym- bol 5 6 7 h unit note min max min max min max min max ras cycle time operation t rc 55 - 60 - 63 - 63 - ns ras cycle time auto refresh t rrc 55 - 60 - 63 - 63 - ns ras to cas delay t rcd 15 - 18 - 20 - 20 - ns ras active time t ras 38.7 100k 42 100k 42 100k 42 120k ns ras precharge time t rp 15 - 18 - 20 - 20 - ns ras to ras bank active de- lay t rrd 10 - 12 - 14 - 15 - ns cas to cas delay t ccd 1-1-1-1-clk write command to data-in delay t wtl 0 -0 -0 -0 -clk data-in to precharge com- mand t dpl 2-2-2-2-clk2 data-in to active command t dal t dpl + t rp dqm to data-out hi-z t dqz 2-2-2-1-clk dqm to data-in mask t dqm 0-0-0-0-clk mrs to new command t mrd 2-2-2-2-clk precharge to data output high-z cl = 3 t proz3 3-3-3-3-clk cl = 2 t proz2 2-2-2-2-clk power down exit time t dpe 1-1-1-1-clk self refresh exit time t sre 1-1-1-1-clk1 refresh time t ref - 64 - 64 - 64 - 64 ms
rev. 1.0 / apr. 2006 12 11 synchronous dram memory 16mbit (1mx16bit) hy57v161610ft(p)-xx(i) series command truth table command cken-1 cken cs ras cas we dqm addr a10/ap ba note mode register set h x l l l l x op code no operation h x hx xx xx lhhh bank active h x llhhx ra v read hxlhlhxca l v read with autopre- charge h write hxlhllxca l v write with autopre- charge h precharge all banks h x llhlx x hx precharge selected bank lv burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x burst-read-single- write hxllllx a9 ball high (other balls op code) mrs mode self refresh 1 entry h l l l l h x x exit l h hx xx x lhhh precharge power down entry h l hx xx x x lhhh exit l h hx xx x lhhh clock sus- pend entry h l hx xx x x lvvv exit l h x x
rev. 1.0 / apr. 2006 13 11 synchronous dram memory 16mbit (1mx16bit) hy57v161610ft(p)-xx(i) series package information 400mil 50pin thin small outline package (tc) 1mx16 synchronous dram 10.059(0.3960) 10.262(0.4040) 11.735(0.4620) 11.938(0.4700) 0.150(0.0059) 0.050(0.0020) 21.057(0.8290) 20.879(0.8220) 0.646 ref 1.2(0.0472) 1.0(0.0394) 0.8(0.0315 bsc) 0.45(0.0177) 0.30(0.0118) 0~5deg gage plane 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0118)

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